With scaling of VLSI circuits, more devices are put into a chip. This not only requires the shrinking of the device size, but it also puts higher requirements on each component of the semiconductor devices.
Reducing equivalent oxide thickness (EOT) of a gate dielectric is important for a metal-oxide-semiconductor (MOS) device to have high performance. Many methods have been explored to reduce the EOT of the gate dielectric. However, when the EOT of a MOS device is reduced, leakage current often increases. Conventionally, this problem is solved by incorporating nitrogen into the gate dielectrics.
The incorporation of nitrogen into the gate dielectrics, however, comes with cost. The carrier mobility of the MOS device is reduced due to the introduction of nitrogen. The drive current of the MOS device is thus reduced, which partially offsets the benefit of the improvement of the equivalent oxide thickness. Among various approaches to compensate for the carrier mobility degradation, rounding the surface of the active regions on which MOS devices are formed is commonly used. As a result, more nitrogen can be introduced (if necessary) into the gate dielectric without concern for reduction of the carrier mobility, so that the performance of the MOS devices can be better adjusted.
In conventional integrated circuit manufacturing processes, surface rounding is performed after the formation of shallow trench isolation regions, and all exposed active regions on a wafer are rounded, including those non-core device regions, which typically do not need to be rounded. This may cause unexpected (adverse) effects on devices formed in those regions. There is the need, therefore, for an improved manufacturing method that restricts the rounding effects locally.